1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device with dual work function gate stacks and a method for fabricating the same.
2. Description of the Related Art
When a transistor is scaled down to improve performance, gate leakage increases while the thickness of a gate dielectric layer is reduced. In order to solve such a problem, the gate dielectric layer has been replaced with a high-k material having a larger dielectric constant than that of SiO2. The high-k material may include metal oxide containing hafnium, zirconium or the like. As the high-k material is adopted, a new problem, that is, a Fermi level pinning effect has occurred. The Fermi level pinning effect is caused by the contact between the high-k material and a polysilicon gate electrode. The Fermi level pinning is a basic characteristic at the boundary between the polysilicon gate electrode and the metal oxide, and increases the threshold voltage of a transistor.
In the transistor, the gate electrode requires a threshold voltage (Vth) for conducting a channel. According to processes of a CMOS device, both of an N-channel transistor and a P-channel transistor may be fabricated. The threshold voltage is influenced by an effective work function. In general, a gate stack includes a gate dielectric layer and a gate electrode, and the gate dielectric layer and the gate electrode determine an effective work function of the gate stack. Furthermore, a gate process may have an effect on the effective work function of the gate stack. The effective work function is distinguished from a work function. The effective work function of the gate stack is a parameter which may be adjusted by the material of the gate dielectric layer, the material of the gate electrode, and the gate stack formation process. On the other hand, the work function of the gate electrode is a specific property of a material. In general, the work function of a specific material (that is, metal layer) corresponds to the value of energy required for discharging electrons within the material into vacuum from atoms of the material, when the electrons are positioned at the Fermi level at the initial stage. The work function has a unit of eV. In general, a gate electrode of an N-channel transistor has an N-type work function lower than a midgap work function, and a gate electrode of a P-channel transistor has a P-type work function higher than the midgap work function.
Recently, in order to solve the Fermi level pinning issue, a gate stack including a high-k material and a metal gate electrode has been adopted. However, during a process for fabricating a CMOS device, it is difficult to form a metal gate electrode having an N-type work function or a P-type work function which requires a threshold voltage suitable for each transistor. Furthermore, although the metal gate electrode having a work function suitable for each transistor is formed, the effective work function of the gate stack may be varied due to various factors caused by the material of the gate dielectric layer contacted with the metal gate electrode and the gate stack formation process (for example, etch process and high-temperature thermal process). Furthermore, the CMOS device may be fabricated by using dual work function metal gate electrodes. In this case, one of the dual work function metal gate electrodes needs to be selectively removed. Accordingly, substantial complexity increases, and the fabrication cost increases.